1. Field of the Invention
The invention relates to semiconductor devices and methods of fabricating the same and more particularly, to semiconductor devices having a pocket line and methods of fabricating the same.
2. Description of the Related Art
A semiconductor device has discrete elements that are subject to a size reduction due to the application of the new high-technology in recent years, on a semiconductor substrate, in order to comply with the demand for increasing high-integration of a semiconductor device. Among the discrete elements, a transistor has been fabricated to be smaller than sub-micron to half-micron grade. The transistor includes gate lines having a doped polysilicon layer and at least one metal layer stacked thereon, spacers placed on the side walls of the gate lines, and source/drain regions formed in a semiconductor substrate and overlapping both ends of the gate lines.
The gate lines typically have a flat-stacked structure on the semiconductor substrate if they are a size greater than or equal to a submicron. However, since gate lines having such a structure may be easily oxidized at their side walls during a semiconductor thermal oxidation process followed by the process of forming the gate lines, this process may result in the gate lines being smaller than the predetermined width and length which were intended at the process of forming the gate lines. Also, the resistance of the gate lines may be increased since the metal layer is oxidized more quickly than the polysilicon layer during the semiconductor thermal oxidation process in the fabrication of the semiconductor device.
One of the methods of forming the gate lines of less than a half micron grade includes forming a trench hole in a semiconductor substrate having a molding layer, forming a gate oxide layer in the trench hole, and allowing the gate lines to contact the trench hole having the gate oxide layer. The gate lines are structured to include a polysilicon layer, a metal layer, and an oxidation stop layer, which are sequentially stacked. Thus, in order to prevent the metal layer from being oxidized during the semiconductor thermal oxidation process, the gate lines have the stacked structure described as above, in which the metal layer is encapsulated by the polysilicon layer and the oxidation stop layer. However, this method is limited in increasing the contact area between the gate lines and the semiconductor substrate as a channel length of the gate lines. The reason is the difficulty of filling the gate lines in the trench hole without voids without adjusting the depth of the trench hole due to the molding layer. Therefore, the contact area between the gate lines and the semiconductor substrate, and the thickness of the molding layer are important considerations for the semiconductor fabrication processes in order to properly place the gate lines in the trench hole.
On the other hand, U.S. Pat. No. 6,159,835 (the '835 patent) discloses an encapsulated low resistance gate structure and method for forming same. According to the '835 patent, the method includes forming a polysilicon layer on a semiconductor substrate having a gate oxide layer, forming a sacrificial layer on the upper surface of the polysilicon layer, forming a trench to expose the polysilicon layer by etching a predetermined portion of the sacrificial layer, and forming a sidewall layer placed on the side walls of the trench and extended to the upper surface of the polysilicon layer.
Then, the method further includes forming a barrier layer on the upper surface of the polysilicon layer, forming a metal layer placed on the barrier layer to partially fill the trench, forming an upper dielectric layer placed on the metal layer, removing the sacrificial layer, and etching the polysilicon layer by using the gate oxide layer as an etch stop layer. At this time, the barrier layer can be formed on the polysilicon layer first before the sacrificial layer is formed.
Because this method provides a gate having a polysilicon layer pattern, a barrier layer pattern and a metal layer pattern, the gate structure shows better resistance characteristics compared to only using one polysilicon layer pattern in the gate
However, while this method may prevent the oxidation of the metal layer pattern by using the polysilicon layer pattern and the upper dielectric layer after forming the gate, it cannot prevent the oxidation of the side walls of the polysilicon layer pattern. Further, because the metal layer pattern is in contact with the sidewall layer pattern, the sidewall layer pattern may be torn off during a subsequent process to oxidize the metal layer pattern.
Therefore, the length of the gate channel can be reduced less than the size of the gate before the oxidation has occurred, and the current driving capability of the semiconductor device having the gate may be decreased.